Hookpad → Verilog Drop-In (Monophonic ROM + Top, SystemVerilog)

Load Hookpad JSON → generate a single-voice ROM and a matching top module that instantiates it and drives AUD_PWM/AUD_SD (100 MHz). Downloads are .sv. No identifier named bit is used.

1) Input

Hookpad JSON file

ROM module name (optional)

…or paste JSON

2) Parameters

Clock (Hz)

Tempo (BPM)

Key (tonic)

Mode

Address wrap

Stats

Drop-in flow: add both files to Vivado → if not auto-detected, set File Type to SystemVerilog → uncomment AUD_PWM/AUD_SD in the Nexys A7 Master XDC → synthesize.

Generated ROM (.sv)

// Your generated monophonic ROM will appear here.

Generated TOP (.sv)

// Your generated drop-in top module will appear here.