SAP-1 Assembler

This assembler targets a minimalist SAP-1 variant with 8-bit instructions: opcode[7:4] + operand[3:0]. The low nibble is either an immediate (use #) or a small address/label (0–15).

Mnemonic	Opcode	Operand	Effect
NOP	0x0	—	No operation.
LDA	0x1	#imm or addr/label	Load A. Immediate: LDA #0xA. Label/address: LDA N0.
ADDI	0x2	#imm	A ← A + imm.
ADDM	0x3	addr/label	A ← A + M[addr].
SUBM	0x4	addr/label	A ← A - M[addr].
STA	0x5	addr/label	Store A → M[addr].
OUTI	0x6	#imm or A	Write to OUT.
OUTA	0x7	—	OUT ← A.
HLT	0xF	—	Halt.

Directives

• .db 0xNN — Emit a data byte. Example: N1: .db 0x64.
• Labels — Name: resolves to address 0x0..0xF (default ROM size).
• Comments — ; or //.

Encoding & Validation Notes

• One byte per line (uppercase hex) for $readmemh. ROM size: 16 by default (set 32/64 in Actions; extra lines are ignored by the 4-bit PC).
• Operand field is 4-bit: values must be 0x0..0xF. Out-of-range inputs highlight in red with a hint.
• Use the Operand selector (Immediate/Label/Address). The Data placeholder and formatting adjust automatically.
• .db helper validates to 0..255 and inserts Label: .db 0xNN or just .db.

Example: OUT = 0xFE (100 + 50 + 104)

    LDA N1
    ADDM N2
    ADDM N3
    OUTA
    HLT

N1: .db 0x64
N2: .db 0x32
N3: .db 0x68

The generated rom16x8.sv embeds the ROM bytes directly (no $readmemh path needed). The sap1_rom.mem file is still exported for reference and tooling.

Keyboard: Press Esc or click outside the card to close.

Using the SystemVerilog pack

1. Click Download SystemVerilog pack in the Actions panel. You’ll receive individual files: sap1_top.sv, sap1_core.sv, rom16x8.sv, sevenseg_hex_mux.sv, btn_debouncer.sv, pulse_stretcher.sv, vga_timing_640x480_ce.sv, vga_hex7_overlay.sv.
2. Create a project folder with this structure (or use the ZIP, below):

   project-root/
     src/
     mem/
     constraints/
     scripts/

3. Place all downloaded .sv files into src/.
4. Download sap1_minimal.xdc and save it to constraints/. Then place your official Nexys-A7-100T-Master.xdc in constraints/ and uncomment only the nets you use.
5. Click Download build_sap1_nexys_a7.tcl and rebuild_after_mem_change.tcl and save them to scripts/.
6. Click Download sap1_rom.mem and save it to mem/sap1_rom.mem.
7. Ensure the ROM path inside the HDL matches your location. The files generated here already point to the value shown in the ROM path hint field (default mem/sap1_rom.mem).
8. Build in Vivado (batch mode) from project-root/:

   vivado -mode batch -source scripts/build_sap1_nexys_a7.tcl

9. After changing only the ROM contents, you can quickly rebuild the bitstream with:

   vivado -mode batch -source scripts/rebuild_after_mem_change.tcl

10. The bitstream will be produced at:

    sap1_nexys_a7/sap1_nexys_a7.runs/impl_1/sap1_top.bit

Using the ZIP bundle

1. Click Download sap1_project.zip. This archive contains:

   src/   (SystemVerilog sources, incl. VGA)
   mem/   (sap1_rom.mem from this page)
   constraints/ (sap1_minimal.xdc)
   scripts/ (build/rebuild TCL)
   README.md

2. Extract the ZIP to your desired project-root/, preserving the folder structure.
3. Copy your Nexys-A7-100T-Master.xdc into constraints/ and uncomment only the nets you use (LEDs, seven-seg, VGA).
4. Build:

   cd project-root
   vivado -mode batch -source scripts/build_sap1_nexys_a7.tcl

5. Fast rebuild after only ROM changes:

   vivado -mode batch -source scripts/rebuild_after_mem_change.tcl

6. Look for the bitstream at:

   sap1_nexys_a7/sap1_nexys_a7.runs/impl_1/sap1_top.bit